1. Field of the Invention
The present invention generally relates to a computer network, and more particularly to a Fast Ethernet receiver with error correction capability.
2. Description of Related Art
Ethernet is a packet-based computer networking that is widely used in constructing a local area network. Fast Ethernet or 100BASE-TX, for example, transfers data at a nominal rate of 100 Mbits/sec.
Fast Ethernet or 100BASE-TX is specified in IEEE 802.3, and may be run over category 5 (CAT5) unshielded twisted-pair (UTP) at 125 MHz symbol rate with segment length of 100 meters. According to Fast Ethernet specification, Fast Ethernet may provide bit error rate (BER) of less than 10−9 without additional forward error control coding (ECC). However, the specified BER cannot be assured oftentimes in real Fast Ethernet due to, for example, aged wiring, multiple segments connection, segment longer than the specified length, cable category lower than CAT5, or non-ideal parameters such as jitter, return loss or rise/fall time.
Data transmission errors may cause loss of a start-of-stream delimiter (SSD) state or loss of an idle state. The data transmission errors may also induce a false idle state or a false packet end. As conventional Fast Ethernet receiver implementation cannot oftentimes provide specified performance, a need has arisen to propose a novel Fast Ethernet receiver with a capability of correcting error without additional forward error control coding (ECC).